VHDL - verschachtelt, wenn Aussagen

Question

ich einen Prozess in VHDL wie folgt definiert haben (ich einige der Bedingungen in wissen, ob Aussagen nicht notwendig sind, aber ich bin, dass für jetzt ignoriert):

LSPflag : process(xcolumn, yrow, picture_q_s) -- output of process depends on xcolumn and yrow 
    variable RGB : RGB_type; -- output colors 
    variable x, y, zx,zy : integer; -- renamed xcolumn and yrow 
    variable isPicture:boolean; 
    begin 
     x:=to_integer(xcolumn); y:=to_integer(yrow); -- convert to integer 
     zy:= To_integer(unsigned(xyoffset)); 
     zx:= (To_integer(unsigned(xyoffset))*XSIZE)/YSIZE; 
     RGB:=BLACK; 
     if zy>360 then 
     --do stuff1 with if statements 
     end if; 
     if zy>240 then 
     --do stuff2 with if statements 
     end if; 
     if zy>120 then 
     --do stuff3 with if statements 
     else 
      isPicture:= x>=EMBORGX+centerx-zx and x<EMBORGX+MEMROWSIZE+centerx-zx and y>=EMBORGY+centery+zy and y<EMBORGY+MEMROWCOUNT+centery+zy;    
      if isPicture and picture_q_s = '1' then--bottomleft corner 
       RGB:=YELLOW or RGB; 
      end if; 
      if y*XSIZE<=-YSIZE*x+YSIZE*XSIZE+(centery-zy)*XSIZE+(centerx-zx)*YSIZE and x>=centerx-zx and x<=XSIZE+centerx-zx and y>=centery-zy and y<=YSIZE+centery-zy then--upperleft corner 
       RGB:=WHITE or RGB; 
      end if; 
      if y*XSIZE>-YSIZE*x+YSIZE*XSIZE+(centery-zy)*XSIZE+(centerx+zx)*YSIZE and x>=centerx+zx and x<=XSIZE+centerx+zx and y>=centery-zy and y<=YSIZE+centery-zy and y*XSIZE<YSIZE*x-(2*zy)*XSIZE then--upperright corner 
       RGB:=RED or RGB; 
      end if; 
      if y*XSIZE>-YSIZE*x+YSIZE*XSIZE+(centery+zy)*XSIZE+(centerx+zx)*YSIZE and x>=centerx+zx and x<=XSIZE+centerx+zx and y>=centery+zy and y<=YSIZE+centery+zy and y*XSIZE>YSIZE*x then--bottomright corner 
       RGB:=BLUE or RGB; 
      end if; 
      if isPicture then 
       picture_address_s <= std_logic_vector(to_unsigned((y-EMBORGY-centery-zy)*MEMROWSIZE + (x-EMBORGX-centerx+zx), picture_address_s'LENGTH)); 
      else 
       picture_address_s <=(others=>'0'); 
      end if; 
     end if; 
     VGA_R<=RGB.R; VGA_G<=RGB.G; VGA_B<=RGB.B; 
    end process; 

ich das Programm wollte zu stoppen, die 4 äußeren Bedingungen zu überprüfen, nachdem es die wahre gefunden hat. Wenn ich es oben schreibe, funktioniert es aber es prüft immer zuerst die drei Bedingungen egal was passiert. Ich habe versucht, so etwas zu tun:

 if zy>360 then 
     --do stuff with if statements1   
     else if zy>240 then 
     --do stuff with if statements2 
     else if zy>120 then 
     --do stuff with if statements3 
     else 
      isPicture:= x>=EMBORGX+centerx-zx and x<EMBORGX+MEMROWSIZE+centerx-zx and y>=EMBORGY+centery+zy and y<EMBORGY+MEMROWCOUNT+centery+zy;    
      if isPicture and picture_q_s = '1' then--bottomleft corner 
       RGB:=YELLOW or RGB; 
      end if; 
      if y*XSIZE<=-YSIZE*x+YSIZE*XSIZE+(centery-zy)*XSIZE+(centerx-zx)*YSIZE and x>=centerx-zx and x<=XSIZE+centerx-zx and y>=centery-zy and y<=YSIZE+centery-zy then--upperleft corner 
       RGB:=WHITE or RGB; 
      end if; 
      if y*XSIZE>-YSIZE*x+YSIZE*XSIZE+(centery-zy)*XSIZE+(centerx+zx)*YSIZE and x>=centerx+zx and x<=XSIZE+centerx+zx and y>=centery-zy and y<=YSIZE+centery-zy and y*XSIZE<YSIZE*x-(2*zy)*XSIZE then--upperright corner 
       RGB:=RED or RGB; 
      end if; 
      if y*XSIZE>-YSIZE*x+YSIZE*XSIZE+(centery+zy)*XSIZE+(centerx+zx)*YSIZE and x>=centerx+zx and x<=XSIZE+centerx+zx and y>=centery+zy and y<=YSIZE+centery+zy and y*XSIZE>YSIZE*x then--bottomright corner 
       RGB:=BLUE or RGB; 
      end if; 
      if isPicture then 
       picture_address_s <= std_logic_vector(to_unsigned((y-EMBORGY-centery-zy)*MEMROWSIZE + (x-EMBORGX-centerx+zx), picture_address_s'LENGTH)); 
      else 
       picture_address_s <=(others=>'0'); 
      end if; 
     end if; 

Aber dann ist es uncompilable und es sagt, wenn Aussage in der Nähe von Text Prozess erwartet wird.

Answer 1

Als BrianDrummond mich erinnerte, war das Problem, dass ich 'else if' anstelle von elsif schrieb.