Warum sehe ich keine Ausgabe, wenn ich synthetisiere?

Question

Ich habe an einer Laboraufgabe gearbeitet, die praktisch abgeschlossen ist, aber ich stoße auf ein Problem, bei dem ich beim Synthetisieren keine Ausgabe sehe. Ich habe 7 Blöcke, die bei einzelnem Test die korrekte Ausgabe anzeigen. Wie kommt es, dass ich bei Verwendung der obersten Modul- und Prüfstandsdateien überhaupt keine Ausgabe bekomme? Unten ist mein Top-Modul, gefolgt von meinem Prüfstand, da ich vermute, dass das Problem da ist. Ich habe es mir angesehen und kann nichts feststellen, was ich falsch gemacht habe. Jede Hilfe wäre willkommen.

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity top_module is port(
    x,y : in std_logic_vector(7 downto 0); 
    opcode : in std_logic_vector(2 downto 0); 
    z : out std_logic_vector(7 downto 0) 
    ); 
end top_module; 

architecture behavior of top_module is 

signal bwAnd, bwOr, bwXor, add, subtract, bwComplement, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6 : std_logic_vector(7 downto 0); 


component BW_And is port(
    x,y : in std_logic_vector(7 downto 0); 
    z1 : out std_logic_vector(7 downto 0) 
    ); 
end component; 

component BW_Rr is port(
    x,y : in std_logic_vector(7 downto 0); 
    z2 : out std_logic_vector(7 downto 0) 
    ); 
end component; 

component BW_Xor is port(
    x,y : in std_logic_vector(7 downto 0); 
    z3 : out std_logic_vector(7 downto 0) 
    ); 
end component; 

component full_adder_8 is port(
    x,y : in std_logic_vector(7 downto 0); 
    cin : in std_logic_vector(7 downto 0) := "00000000"; 
    sum, cout: out std_logic_vector(7 downto 0) 
    ); 
end component; 

component full_subtractor_8 is port(
    x,y : in std_logic_vector(7 downto 0); 
    cin : in std_logic_vector(7 downto 0) := "11111111"; 
difference, cout: out std_logic_vector(7 downto 0) 
    ); 
end component; 

component Complement is port(
    x : in std_logic_vector(7 downto 0); 
    z4 : out std_logic_vector(7 downto 0) 
    ); 
end component; 

component mux is port(
    z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0); 
    opcode : in std_logic_vector(2 downto 0); 
    mux_out : out std_logic_vector(7 downto 0) 
    ); 
end component; 

begin 

--instantiating components and mapping ports 

c0: BW_And port map(x => x, y => y, z1 => bwAnd); 

c1: BW_Or port map(x => x, y => y, z2 => bwOr); 

c2: BW_Xor port map(x => x, y => y, z3 => bwXor); 

c3: full_adder_8 port map(x => x, y => y, sum => add); 

c4: full_subtractor_8 port map(x => x, y => y, difference => subtract); 

c5: Complement port map(x => x, z4 => bwComplement); 

c6: mux port map(z1 => mux_in1, z2 => mux_in2, z3 => mux_in3, sum => mux_in4, difference => mux_in5, z4 =>mux_in6, opcode => opcode, mux_out => z); 

end behavior; 

Prüfstand:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity Lab4 is 
end Lab4; 

architecture behavior of Lab4 is 

component top_module is port(
    x,y : in std_logic_vector(7 downto 0); 
    opcode : in std_logic_vector(2 downto 0); 
    z : out std_logic_vector(7 downto 0) 
    ); 
end component; 

signal test_x : std_logic_vector(7 downto 0); 
signal test_y : std_logic_vector(7 downto 0); 
signal test_opcode : std_logic_vector(2 downto 0) := "000"; 
signal test_z : std_logic_vector(7 downto 0); 

begin 

    uut: top_module port map (x => test_x, y => test_y, opcode => test_opcode, z => test_z); 

sim_proc : process 
begin 

    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "000"; 
    wait for 100 ns; 
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "001"; 
    wait for 100 ns; 
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "010"; 
    wait for 100 ns; 
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "011"; 
    wait for 100 ns; 
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "100"; 
    wait for 100 ns; 
    test_x <= "00010100"; test_y <= "11001111"; test_opcode <= "101"; 

end process; 
end behavior; 

Entities für jede Komponente:

entity BW_And is port(
    x,y : in std_logic_vector(7 downto 0); 
    z1 : out std_logic_vector(7 downto 0) 
    ); 
end BW_And; 

entity BW_Or is port(
    x,y : in std_logic_vector(7 downto 0); 
    z2 : out std_logic_vector(7 downto 0) 
    ); 
end BW_Or; 

entity BW_Xor is port(
    x,y : in std_logic_vector(7 downto 0); 
    z3 : out std_logic_vector(7 downto 0) 
    ); 
end BW_Xor; 

entity full_adder_8 is port(
    x,y : in std_logic_vector(7 downto 0); 
    cin : in std_logic_vector(7 downto 0) := "00000000"; 
    sum, cout: out std_logic_vector(7 downto 0) 
    ); 
end full_adder_8; 

entity full_subtractor_8 is port(
    x,y : in std_logic_vector(7 downto 0); 
    cin : in std_logic_vector(7 downto 0) := "11111111"; 
    difference, cout: out std_logic_vector(7 downto 0) 
    ); 
end full_subtractor_8; 

entity Complement is port(
    x : in std_logic_vector(7 downto 0); 
    z4 : out std_logic_vector(7 downto 0) 
    ); 
end Complement; 

entity mux is port(
    z1,z2,z3,sum,difference,z4 : in std_logic_vector(7 downto 0); 
    opcode : in std_logic_vector(2 downto 0); 
    mux_out : out std_logic_vector(7 downto 0) 
    ); 
end mux; 

Answer 1

Ich erkannte, wo mein Problem doch war. Das Problem war mit meiner Mux-Datei. In meinem Prozess habe ich nur "Opcode" übergeben und dabei alle Eingaben vernachlässigt.

Vorher:

process (opcode) 
    . 
    . 
    . 
end process; 

Nach:

process (z1,z2,z3,sum,difference,z4,opcode) 
    . 
    . 
    . 
end process;